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Post by StRiDeR on Feb 11, 2004 21:01:31 GMT 8
WARNING!!!www.microsoft.com/technet/security/bulletin/MS04-006.asp "A security vulnerability exists in the Windows Internet Naming Service (WINS). This vulnerability exists because of the method that WINS uses to validate the length of specially-crafted packets. On Windows Server 2003 this vulnerability could allow an attacker who sent a series of specially-crafted packets to a WINS server to cause the service to fail. Most likely, this could cause a denial of service, and the service would have to be manually restarted to restore functionality."
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Post by atokENSEM on Feb 11, 2004 22:44:20 GMT 8
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Post by StRiDeR on Feb 12, 2004 20:40:37 GMT 8
Intel Prescott Pentium 4 Processor = cpu baru?
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The German strategist Helmut von Moltke once said, "No plan survives contact with the enemy."
That adage is certainly true in the technology world. In Intel's ideal world, the company would have had all the time it needed to tweak and perfect its 90nm process. Rumors over the last few months pointed to teething problems with the new process, including higher operating temperatures and power consumption than had been expected with Intel's strained silicon process. The net result has been a somewhat restrained launch for Intel's new progeny. Initial plans had called for launching the 3.4GHz CPU in quantity, but yields of 3.4GHz Prescotts have apparently been quite low. One of Intel's biggest OEMs scaled back its system offerings to not include Prescott-based systems in one product category due to the lack of 3.4GHz Prescott availability.
On top of that, AMD has been on a roll. The recent release of the Athlon 64 3400+ proved to be a pleasant surprise, offering better performance gains than anticipated -- a rarity these days. Sales of the new Athlon 64 line have propelled AMD to its first quarterly profit in over a year. Performance enthusiasts have been buzzing about AMD's new flagship CPUs.
As we noted, Intel originally planned to launch its new 90nm Pentium 4 with a top clock rate of 3.4GHz. In fact, Intel may still paper launch at 3.4GHz, but only 3.2GHz and slower parts will be widely available. Supplies of the 3.4GHz Prescott will be "low," and Intel will likely say so during its launch events.
To fill the gap, Intel is also launching a pair of new Pentium 4's built around the older Northwood generation technology. One is a standard Northwood-based CPU, with 512KB of L2 cache, while the other will be an update to the Pentium 4 Extreme Edition (dubbed by some pundits as the "Emergency Edition"). Like the first P4EE, the new chip sports 512KB of L2 cache and 2MB of L3 cache. Both of the new/old CPUs will ship at 3.4GHz. All Prescott CPUs shipping on February 2nd will support Hyper-Threading and an 800MHz FSB (200MHz actual FSB clock, quad-pumped).
Intel supplied ExtremeTech with two processors: a 3.4GHz Pentium 4 Extreme Edition and a 3.2GHz Prescott CPU. Given that, it would be interesting to compare the performance of a 3.4GHz Northwood to Intel's new baby. We sorely wanted to do this, but Intel was understandably reticent to hand out old-generation CPUs that might "distract" from the launch of their new architecture. However, we were able to obtain a 3.4GHz Northwood from another source, so we have performance data for a nearly complete suite of new CPUs to present -- only the rare 3.4GHz Prescott is missing from the mix.
Before we get to the performance tests, though, let's take a stroll through Prescott's internal architecture. The new CPU is more than a die shrink, adding some significant architectural enhancements.
Prescott is more than just a die shrink. When Intel moved to the 130nm process with Northwood, designers added an additional 256KB of L2 cache and fine-tuned a dormant feature present in all P4's existing since the original "Willamette" design: the ability to perform simultaneous multitasking, which Intel dubs Hyper-Threading. Initially, Hyper-Threading was disabled in Northwood chips, but turned on when Intel launched the 3.06GHz version.
Moving to 90nm, Intel has once again enhanced the microarchitecture. Prescott has a number of tweaks, some simply to take advantage of the new process, while others are actually changes to the internal architecture. The most obvious change, brought about by the reduced die size available at 90nm, is the additional cache. Both the L1 and L2 cache sizes have doubled. The L1 data cache is now 16KB, while the L2 unified (data and instruction) cache size is now 1MB. Let's take a quick look at how the various Intel Pentium 4 CPUs compare, and toss in an Athlon 64 for comparison.
Current Feature Set (2/2/04) Willamette Northwood P4EE Prescott Athlon64 (FX-51 & 3400+)
Process 180nm 130nm 130nm 90nm 130nm
Transistor Count (Million) 42 55 178 125 106
Die Size (mm2) 170 131 237 112 193
L1 Cache (KB) 8 8 8 16 128
L2 Cache (KB) 256 512 512 1024 1024
L3 Cache (KB) NA NA 2048 NA NA
Max Frequency 2/2/04 2GHz 3.4GHz 3.4GHz 3.2GHz (3.4GHz
soon) 2.2GHz
The die shrink enables Intel to build a processor with double the cache of Northwood, but with a smaller die size. Intel has also aggressively moved to 300mm wafers, so the net result is a much lower cost per CPU manufactured. Of course, the cost of transitioning to new fabrication technologies still has to be amortized, but the long term result is lower costs, and eventually, lower prices.
We covered the original Pentium 4 architecture extensively two years ago, so our discussion here focuses on changes to the architecture inherent in Prescott.
Intel's CPU architects weren't content with simply shrinking the CPU and adding more cache. The underlying philosophy of the Pentium 4 is to scale performance by increasing the clock frequency. One method for enabling higher clock rates is to increase the number of pipeline stages (more stages yield less circuit propagation delay per stage, permitting higher clock rates). A deeply pipelined architecture needs to have fairly good knowledge of what instructions are likely to enter the pipeline in the near future. Further, most software these days isn't just linear streams of code, but often loops and branches, as needed by the application.
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Post by StRiDeR on Feb 12, 2004 20:42:10 GMT 8
The ability to predict when code will branch, and hence know what code will enter the pipeline, is known as branch prediction. A deeply pipelined architecture needs to have highly accurate branch prediction. If the pipeline is filled with incorrect instructions and has to be flushed and reloaded with proper instructions due to an unpredicted code branch, the performance penalty can be pretty stiff. For example, a pipeline flush in Northwood results in a 20 cycle performance penalty.
The pipeline in Prescott has been extended to 31 stages, so a pipeline flush due to poor branch prediction can result in a much larger clock cycle penalty every time a branch misprediction occurs. Therefore Intel's architects worked to improve Prescott's branch prediction over that of Northwood.
Prescott has a few areas of enhancement in branch prediction functionality. Before we get into details, understand that all P4 processors actually have two areas where branch predictions are performed -- in the front end of the pipeline, where x86 instruction streams are loaded, and at the trace cache (L1 instruction cache containing micro-ops). Most instruction sequences are retrieved from the trace cache during normal program execution. The pipeline depth (20 or 31 stages mentioned prior) is measured from the point of obtaining the trace cache instruction pointer from the Branch Target Buffer (BTB) associated with the trace cache. You can see this BTB in the block diagram has 2K entries (up from 512 entries in older P4s) versus 4K entries for the front-end BTB (same as older P4s).
Static branch prediction (a technique that relies on prior knowledge of branch behavior before actual program execution, such as knowing most loops branch backwards) was improved in Prescott. In all P4's, static branch prediction will occur at decode time if the Branch Target Buffer (BTB) has no dynamic branch prediction data for a particular branch. In prior P4 static branch prediction algorithms, backwards branches were assumed to be part of loops, but that's not always the case. Prescott adds logic to help determine if a backward branch was part of a loop or another type of backwards branch. Loop branches tend to have shorter jumps than other types of backward branches. If the branch was not included in the BTB and must be statically predicted, a check is made on both branch direction and branch distance. If a predetermined threshold for branch distance (seen in typical loops) is exceeded, the branch is predicted to be not taken. In other cases, it was determined that certain conditions would typically result in not taken branch behavior, regardless of distance and direction.
Dynamic branch prediction accuracy is enhanced by adding an indirect branch predictor. Interestingly, this is similar to a technique used in the Pentium-M (Banias) processor. Intel's trace data revealed that the new techniques improved branch prediction in a number of SPEC benchmark from 2 - 20%.
The Prescott architecture team incorporated additional tweaks to the new Pentium 4 microarchitecture. The L1 data cache associativity was increased from 4-way to 8-way when the size doubled (8K in Northwood to 16K in Prescott). The new 1MB unified, write-back L2 cache is still 8-way set associative, as in past P4s, and still has 128 bytes/cache line.
The size of the instruction schedulers for x87 and all levels of SSE instructions were increased to improve the ability to find parallelism in multimedia code, as were the effective size of the queues that feed all the schedulers, not just a subset. Increasing scheduler queue size reduces allocator stalls, permitting the allocator logic to continue assigning micro-ops to individual functional unit scheduler queues that follow in the pipeline, while also processing machine resource requests from new micro-ops entering the allocator stage.
Prescott Brings More Cache to Intel's Future (PC Magazine)
Update: Intel Launches Prescott
Dealers Begin Tipping Prescott Prices, AMD Cuts
A dedicated integer multiplier has been added. Previously, the floating point multiplier had been used for integer multiplies, but that increased latency by moving operands to the FP unit and routing the result back to the integer unit.
More types of micro-ops can now be encoded inside the trace cache than in prior P4s, rather than being sequenced by the Microcode ROM (a slow process for complex and/or infrequently used instructions). Two common instruction types that can now be encoded and stored in the trace cache are indirect calls with a register source operand, and software prefetch instructions.
Additional processor resources were incorporated, including the ability to have 32 stores outstanding (versus 24 in past P4s) and increasing the number of write combine buffers to eight (from six). The processor also keeps track of eight loads that missed the L1 data cache; previously, only four missed loads were tracked. Some changes were made to the hardware prefetch mechanism to increase its efficiency, in addition to software prefetches now being stored in the trace cache.
Shift and rotate instructions can now be executed quickly by a new shifter/rotator logic block included in one of the two fast ALUs. In prior P4s, such operations were complex and took many cycles.
Sequencing of load and store micro-ops (instructions) was reworked in Prescott to avoid latency and load re-execution. This occurred when store data is required to be forwarded to a load instruction (prior to storing to the L1 data cache), yet the load micro-op executes prior to the store micro-op. Prescott adds a predictor to indicate a load is likely to need data forwarded from a particular store micro-op, and the load scheduler can hold the load until the specific store is scheduled.
Most of these seem like relatively minor increases in efficiency, but they all serve to also improve Hyper-Threading performance. In fact, some of these changes may have little effect if only a single thread is running, but affect performance in a multithreaded environment. Some additional resources were added to specifically improve performance in a threaded environment, such as the ability to simultaneously access the memory page table while handling a memory access that splits a cache line.
SSE3 Instructions
The new 90nm Pentium 4 adds 13 new SSE instructions, aka "Prescott New Instructions." These include:
An instruction to speed up x87 floating point to integer conversion
Five instructions to improve the efficiency of loading, moving and duplicating SIMD data, useful in complex arithmetic algorithms
An instruction to avoid cache line splits when loading data, useful in certain video compression applications
Four instructions to enable more efficient handling of arrays of structures. This is useful in 3D graphics, particularly when processing vertex buffers.
Two instructions that help manage thread synchronization, which will in turn improve Hyper-Threading performance.
Like past additions to the SSE instruction set, applications will need to be recompiled -- and in some cases, hand-tuned -- to take advantage of the new instructions. Since Prescott has been sampling for a number of months now, the wait for some key applications may not be too long. More detailed information on SSE3 is available on Intel's developer site
*copy/paste
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Post by enigma on Feb 12, 2004 22:10:08 GMT 8
lom lg.....ingat dh nk mulakan edisi siasat..... tp orgnya jauh nun di sini.....apapun kita tunggu dan lihat jer... |
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Post by atokENSEM on Feb 14, 2004 16:56:50 GMT 8
lom lg.....ingat dh nk mulakan edisi siasat..... tp orgnya jauh nun di sini.....apapun kita tunggu dan lihat jer... edisi siasat utk sape?  new news.. tahun 2005,computer sume harga bawah seribu..atok tak pasti samada betul ke tak berita ni..krn kwn atok yg mengajar di upm..kwn die yg bgtau! |
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Post by StRiDeR on Feb 15, 2004 1:02:49 GMT 8
edisi siasat utk sape? new news.. tahun 2005,computer sume harga bawah seribu..atok tak pasti samada betul ke tak berita ni..krn kwn atok yg mengajar di upm..kwn die yg bgtau! emm, betul ke tahun 2005, harga komp. bawah seribu?...naper harga dia leh turun sampai cam tue?...ader sebab ke? |
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LaNgSuIr
Senior Student
Jangan takutkan pada hantu..amalkan takut pada tuhan..
Posts: 310
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Post by LaNgSuIr on Feb 15, 2004 4:22:46 GMT 8
tul ke nih!macam tu aku tak jadi beli lah pc baru sehingga 2005!
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Post by enigma on Feb 15, 2004 16:45:37 GMT 8
emm, betul ke tahun 2005, harga komp. bawah seribu?...naper harga dia leh turun sampai cam tue?...ader sebab ke? itulah yg peliknya....mcm mn harga dia bleh turun banyak camtu? |
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Post by StRiDeR on Feb 15, 2004 19:35:36 GMT 8
itulah yg peliknya....mcm mn harga dia bleh turun banyak camtu? tue la pasal..nie aku nak tanya kat atok nie...nak confirm kan... |
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Post by atokENSEM on Feb 15, 2004 19:44:47 GMT 8
iyela..sbb hal ni dah tersebar kat MMU..ape lak byk sgt turun..skit je..bape2 ratus je..lgpun comp skrg ni rm2000 pun dah leh dpt..
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Post by StRiDeR on Feb 15, 2004 19:50:14 GMT 8
iyela..sbb hal ni dah tersebar kat MMU..ape lak byk sgt turun..skit je..bape2 ratus je..lgpun comp skrg ni rm2000 pun dah leh dpt.. ye la...x kan harga turun tanpa sebab kot...mesti ader sebab dia kan?...leh atok bagitau x sebab dia? |
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Post by atokENSEM on Feb 15, 2004 20:13:52 GMT 8
ye la...x kan harga turun tanpa sebab kot...mesti ader sebab dia kan?...leh atok bagitau x sebab dia? sebab die..zaman skrg ni kan,zaman IT..so..di skolah pun guna comp!jadi kementerian akan..kurangkan harga computer..agar sume rakyat dpt memiliki computer dgn harga yg murah..skrg ni,govn dah buat..pembelian computer kat pejabat pos kan..harga disitu pun..lbh krg murah gak! |
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Post by StRiDeR on Feb 15, 2004 21:26:43 GMT 8
sebab die..zaman skrg ni kan,zaman IT..so..di skolah pun guna comp!jadi kementerian akan..kurangkan harga computer..agar sume rakyat dpt memiliki computer dgn harga yg murah..skrg ni,govn dah buat..pembelian computer kat pejabat pos kan..harga disitu pun..lbh krg murah gak! ooo, cam tue...skang baru lah jelas... |
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Post by atokENSEM on Feb 16, 2004 1:03:41 GMT 8
ooo, cam tue...skang baru lah jelas... nape,td tak jelas ke?kalo masih tak jelaskan lagi..atok leh menambah..  |
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